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# Normalizing Three-Divide Operands in One Cycle

IP.com Disclosure Number: IPCOM000105052D
Original Publication Date: 1993-Jun-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 70K

IBM

## Related People

Spencer, AK: AUTHOR

## Abstract

In the division algorithm A/B and A=Q*B + R one of the requirements is that the operands be normalized before the converging algorithm can begin. The dividend and divisor must be normalized numbers of the form:

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Normalizing Three-Divide Operands in One Cycle

In the division algorithm A/B and A=Q*B + R one of the
requirements is that the operands be normalized before the converging
algorithm can begin.  The dividend and divisor must be normalized
numbers of the form:

1/2 <= A < 1
1/2 <= B < 1

Note that one of the requirements is that the numbers be
positive.  Since the divide instructions defined in the POWER
architecture are signed divisions, we will have both positive and
negative numbers entering the divide logic.

The POWER architecture defines two divide instructions, (div
and divs).  The first is a 64 bit dividend divided by a 32 bit
divisor, also know as divide long.  The 64 bits for this instruction
are formed by concatenating the RA operand with the MQ register.  The
second is a 32 bit dividend divided by a 32 bit divisor, also known
as divide short.

In the division hardware both of these instructions are treated
the same.  If a divide short instruction is decoded then its RA
operand is sign extended to 64 bits to make it look like a divide
long instruction.

Since there are three 32 bit quantities that make up the
operands for the divided instructions it could take as many as three
cycles to convert these operands into positive numbers.  The
conversion would be accomplished by performing a two's complement
operation of each one and based on the sign of the operand, storing
the operand or the output of the two's complement logic.  This
procedure would be repeated once for each 32 bit quantity.  Since the
performance of this algorithm was to exceed that of the RISC
System/6000* a 3 cycle penalty for converting the operands was
excessive.

The...