Browse Prior Art Database

Floating Point Add/Subtract Instruction Performance Enhancement

IP.com Disclosure Number: IPCOM000105245D
Original Publication Date: 1993-Jul-01
Included in the Prior Art Database: 2005-Mar-19
Document File: 2 page(s) / 85K

IBM

Related People

Repka, SJ: AUTHOR [+1]

Abstract

Described is a technique to improve the performance of floating point add/subtract instructions by:

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Floating Point Add/Subtract Instruction Performance Enhancement

Described is a technique to improve the performance of floating
point add/subtract instructions by:

o   Predicting if a post-normalization cycle is required, and
o   Eliminating the recomplement cycle when the signs are unlike and
exponents not equal.

In high performance system implementations, four machine cycles
are required to execute the floating point add/subtract instructions
when the signs are equal and exponents are not equal.  Five machine
cycles are required when the signs are not equal and exponents are
not equal.  In the former case, the post-normalization cycle is
always taken.  In the latter case, a recomplement cycle is,

For the case of the signs equal and the exponents not equal,
the post-normalization cycle is saved.  The cycle is taken only for
the case when the sum of the leading digits is equal to 'F' x 'O' x.
This shorter algorithm is used when it has been determined that
post-normalization is not required.

Improvement is achieved as follows:

1.  A post-normalization prediction in the first execution cycle
determines if a shorter algorithm is to be used.
2.  When the short algorithm is used, the shift amount to align the
smaller operands fraction will be modified.
3.  A decision to block the "hot" carry for the subtract case is
based on the value of a guard digit.  Recomplementation is not
needed.

The guard digit is required by 370 architecture for added
precision.  In a previous floating point long implementation, the
guard digit is provided in bits 60-63 by shifting left the larger
operand (56 bits) one digit and forcing O's into bits 60-63.  The
fraction becomes 60 bits wide.  When preshifting the smaller operand
to align the exponents, the least significant digits are shifted out.
The guard digit, thus gives the ability to preserve an extra digit
position.  This implementation always required the post-normalization
cycle to shift out the guard digit from the 60 bit fraction and,
thus, generating the necessary 56 bit result.  The complement cycle
was also always taken to take care of the situation where the large
operand was 2's complemented.  The capability to determine this and
recomplement it was not available.

The implementation described here solves the above...