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Minimum Run-Length Pattern Generator

IP.com Disclosure Number: IPCOM000106240D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 233K

IBM

Related People

Rider, SH: AUTHOR

Abstract

Disclosed is a method of generating deterministic limited run-length patterns suitable for testing memories or digital communications devices.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Minimum Run-Length Pattern Generator

Disclosed is a method of generating deterministic limited
run-length patterns suitable for testing memories or digital
communications devices.

patterns of minimum run-length.  In fact, the run-length will be 2,
the smallest run-length possible without periodicity.  To do this,
the generator is designed to change its pattern after every 2supn
symbols.  This means that every 2 symbols, every 4 symbols, every 8
symbols, etc. will have 1's and 0's switching at different times.
The method for generating the patterns is described in Fig. 1.

This algorithm will create a sequence of 1's and 0's that will
invert every time the counter hits a 2supn boundary.  (Invert is not
actually correct.  The sequence increments on every qn boundary where
2 (binary numbers) where increment and invert are the same.)  For
example, if the counter were allowed to proceed to 64, the sequence
generated would be (even parity used):

Beginning(0)     ----------------------------------------->
end(63)
0110 1001 1001 0110 1001 0110 0110 1001 1001 0110 0110 1001 0110 1001
1001 etc.

Here, the first two are the inverse of the next two, the first
4 the inverse of the next 4, first 8 are the inverse of the next 8,
etc.  Note that the sequence generated is run-length limited to 2;
that is, there will never be more than two consecutive 1's or 0's
coming out of the generator.

Although the most practical use of this algorithm is in the
binary number system, it can be generalized to any other system.  For
example, in Base-3 the XOR function is replaced by base-3 addition
(the XOR operation is really base-2 addition) across a base-3 counter
and the properties of the patterns will remain the same.  The maximum
run-length will still be 2 and the patterns will now be non-3supn
periodic.

To use this algorithm to generate m-bits wide, the output of
the parity generator is put into an m-bit shift register (Fig. 2).

This is the circuit that generates the patterns shown in Fig.
6. ...