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Optimal Net Ordering for Via Noise Manimization in TCM Design

IP.com Disclosure Number: IPCOM000106303D
Original Publication Date: 1993-Oct-01
Included in the Prior Art Database: 2005-Mar-20
Document File: 4 page(s) / 192K

IBM

Related People

Chen, HH: AUTHOR [+2]

Abstract

Disclosed is a net ordering and layer assignment method to minimize via noise in thermal conduction module (TCM) design.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 35% of the total text.

Optimal Net Ordering for Via Noise Manimization in TCM Design

Disclosed is a net ordering and layer assignment method to
minimize via noise in thermal conduction module (TCM) design.

In the design of thermal conduction modules [*], chips are
interconnected through thin-film layers and glass-ceramic layers.
The mutual inductance and capacitance between adjacent signal lines
may generate near-end coupled noise on the driver's side and far-end
coupled noise on the receiver's side.  To prevent the circuits from
false switching, it is important to complete the wiring without
introducing excessive noises.  There are two components which
determine the total coupled noise; namely, the XY noise and VIA
noise.  The XY noise is the coupled noise between adjacent signal
lines in the X or Y direction.  The VIA noise is the coupled noise
between adjacent pins or vias in the Z direction (Fig. 1).  In the
past, the research was mostly focused on the crosstalk of XY noise,
while the problem of VIA noise has not been well studied.  This
invention identifies the importance of the via noise problem and
proposes a novel sorting algorithm to minimize the via noise for TCM
design.

The VIA noise can be represented by a function of DIST and LC,
where
DIST = sqrt < (DELTA X) sup 2 + (DELTA Y) sup 2> is the XY distance
between the pins (vias), and LC is the via coupled length in the Z
direction.  In order to minimize the VIA coupled noise, we can either
increase DIST, the distance between vias, or reduce LC, the coupled
length.  To increase the distance between vias, we have to optimize
the pin locations and hybrid via assignment.  The pin or via location
should be selected only if the estimated XY noise and VIA noise for
this net are within the noise limit.  When all the pin and via
locations are determined, the only other variable which can change
during wiring is the coupled length LC between adjacent vias.

The via coupled length LC is determined by the wiring layer of
each net.  In order to reduce the coupled length between adjacent
vias, one of the connections which have pins on the top surface
should be wired on the higher planes to shorten the via.  The
importance of wiring plane selection for via noise minimization can
be illustrated by a simple example in Fig. 2.  If connections A,B are
wired on the bottom planes, and connections C,D are wired on the top
planes, the via coupled noise between A and B will be maximal.
However, if the wiring planes for A and D are swapped, the via noise
between A and B can be reduced without affecting the number of
connections on each layer.  Based on this observation, for two
connections with adjacent pins, it is desirable to wire at least one
of them on the higher planes to reduce the via noise.  This layer
assignment problem is similar to a one-dimensional placement problem,
where the coupled noise between adjacent vias can be treated as an
expulsion force to separate th...