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Merged Phase-Locked Loop and Frequency-Chopper Disclosure Number: IPCOM000106429D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 63K

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Emeigh, R: AUTHOR [+4]


A Phase-Locked Loop (PLL) is described which merges a ring-oscillator with a frequency-chopper. This has the advantage of reducing the frequency of the ring oscillator by a factor of four without a reduction in the output frequency.

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Merged Phase-Locked Loop and Frequency-Chopper

      A   Phase-Locked   Loop  (PLL)  is  described  which  merges  a
ring-oscillator with a frequency-chopper.  This has the advantage  of
reducing  the  frequency  of  the ring oscillator by a factor of four
without a reduction in the output frequency.

      Fig. 1  shows  a  PLL  consisting  of  three  parts:    A  Ring
Oscillator,  1,  a  Frequency Chopper, 2, and a Loop Control, 3.  The
Phase-Frequency Detector (PFD), 12, compares the  input  waveform  at
node  G to the feedback signal at H.  The PFD output gives pulses out
to increase or decrease  the  frequency  as  required  to  match  the
frequencies  at  G  and  H.    The  Pulses  generated  by the PFD are
converted to current pulses by the Charge-Pump, 13.  The Filter,  14,
averages the pulses, and the Driver, 15,  buffers the filter voltage.

      The  Ring Oscillator is composed of four variable-delay stages,
4,5,6,7.  The frequency of the Ring Oscillator  varies  up  and  down
with  the  Loop  Control  output,  node  V.    Once frequency-lock is
achieved, the frequencies of nodes G and H are the same.

      In previous implementations without  the  chopper,  the  output
signal, E, is taken from an output of the Ring Oscillator  (at node A
or  B  or C or D).  The Divider, 16, would then divide the oscillator
frequency by a fixed number (N equals 2, or 4,  or  8,  et...