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Automatic Fault Model Generation Disclosure Number: IPCOM000106445D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 2 page(s) / 89K

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Dibrino, M: AUTHOR [+3]


Disclosed is a technique that generates accurate fault models for high density transistor circuits automatically.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Automatic Fault Model Generation

      Disclosed is a technique that generates accurate fault models
for high density transistor circuits automatically.

      Computer industry has become so competitive that the boundaries
between the main-frame, mini-computer and workstation has become
unclear.  High performance VLSI circuits with millions of
transistors, such as CPU chips, require custom design to achieve very
aggressive timing and functional goals.

      A conventional 'book library' approach whereby each book
contains a limited number of transistors is no longer applicable for
custom design.  For example, a custom designed multiplexer circuit
contained within a fixed-point unit may not be usable in a floating
point unit.  In such a fully-custom design approach there can no
longer be any 'shared books' among different design units.

      As the number of transistors in each custom design increases to
a degree, say several thousands to several millions, it is obvious
that conventional 'manual' or 'semi-automatic' fault modeling is no
longer a feasible approach.

      Disclosed is technique and algorithm that generate fault models
directly from a VLSI design database is described.  This technique is
able to generate an accurate fault model for VLSI circuits of
unlimited size hierarchically.  Currently, this algorithm is
implemented in several platforms and is able to automatically
generate fault models for a custom-designed circuit with several
hundred-thousand transistors.

      Summary of Algorithm - A VLSI design system provides tools that
allow circuit designers to implement their circuit design either at
the transistor level or in a hierarchical structure.  Through
schematic entry, circuit designers will perform circuit simulation,
optimization, etc. to accomplish their custom design.  The size of
circuits could range from several thousand transistors to several
million transistors.  The final design will present itself as a
layout format.  The VLSI design system also provides a powerful
feature to convert this layout to a netlist format.

      Our fault modeling procedure starts with a netlist format.  An
internal netlist format is first defined to accommodate various
netlists available in the industry.  A 'front-end' translation
program is used to accomplish this task.

      Now, there is an interconnected 'sea of transistors'.  These
interconnected transi...