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Large Arrays without Redundancy Fusing Disclosure Number: IPCOM000106540D
Original Publication Date: 1993-Nov-01
Included in the Prior Art Database: 2005-Mar-21
Document File: 4 page(s) / 105K

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Related People

Kopp, A: AUTHOR [+2]


This article describes a concept for using fixable arrays' redundancy dynamically, without integrated fuses.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Large Arrays without Redundancy Fusing

      This article describes a concept for using fixable arrays'
redundancy dynamically, without integrated fuses.

      Large arrays, either as standalone memory chips or embedded on
logic chips, contain redundancy to prevent chips from being thrown
away in case a test is not completely successful.  Redundant
word-lines of the array are enabled, bad word-lines at the same time
disabled by blowing one or more fuses by laser light.

      The newest generation of IBM's CMOS IV arrays contain a so
called Array Built-In SelfTest (ABIST).  This test methodology
initializes a Finite State Machine (FSM) of each array with the
appropriate information using a scan chain.  Once the arrays have
been initialized, it is an iterative process to pulse a couple of
clocks until the largest array has finished testing.  The FSM of the
smaller arrays will enter a 'WAIT' state when completed until the
test of the larger arrays have finished.  Within the embedded array,
SRLs are present to hold certain information while the FSM is being
pulsed to test the array.  Each array has a Pass/Fail SRL.  For
arrays with redundancy, a Fixable SRL exists, and also some
additional SRLs, organized in banks, which hold the failing addresses
to be repaired.  When the FSM encounters a fail, the Pass/Fail bit
will be 'turned on'.  If this failing array has redundancy, the
failing address will be placed into one of the redundant banks.  If
the redundant banks are full and the FSM encounters another fail, the
Fixable bit will be 'turned on' to indicate this array is NOT
fixable.  At the end of the test, a scan out of all the Pass/Fail
bits (along with the Fixable and Redundant SRL bits) is performed.

      External software analyzes the fail data to determine which
chips are repairable and which word lines need to be repaired.  A
chip is considered repairable if the number of failing word lines
does not exceed the number of redundant word lines within the array.
For each repairable chip, the failing addresses are converted into a
fuse string which represents which fuses need to be blown.  The bit
positions of the failing address that are in the 'on' state are the
positions within the fuse string that are to be activated.  For

           An array has 256 word lines (8 bit addresses)
           Failing word line => 00101101 (45 decimal)
                                7<-----0 (position)

           The fuse string would indicate to blow p...