Array Testing with Minimal Hardware
Original Publication Date: 1992-Jun-01
Included in the Prior Art Database: 2005-Mar-22
Publishing Venue
IBM
Related People
Abstract
Disclosed is a method for testing embedded arrays on a chip with minimal dedicated test hardware.
Array Testing with Minimal Hardware
Disclosed is
a method for testing embedded arrays on a
chip with minimal dedicated test hardware.
In order to
deliver a defect-free chip, all embedded arrays
must be fully tested. The most time
efficient way of accomplishing
this is to test all arrays in parallel.
While parallel testing may
be the fastest method, it also requires that a large area of the chip
be dedicated to test hardware. Each array would require a dedicated
test input latch, as well as a dedicated test output latch.
Instead of
having dedicated test hardware for each array, a lot
of that hardware can be shared by multiple arrays. A single test
input latch can be used to source multiple arrays. A single test
output latch can be used to observe the outputs of multiple arrays.
This is
accomplished by decoding the upper address bits to
control the muxing of array outputs to a single test latch as shown
in the figure.