High Speed Bus
Original Publication Date: 1992-Jul-01
Included in the Prior Art Database: 2005-Mar-23
Edwards, L: AUTHOR [+1]
This article describes a high-speed multimaster bus similar to the VME Bus. The high-speed bus incorporates components of the VME Bus with certain key enhancements to improve performance and reduce the card logic required to drive the backplane. The high-speed bus will hereafter be referred to as the "bus".
High Speed Bus
describes a high-speed multimaster bus
similar to the VME Bus. The high-speed bus incorporates components
of the VME Bus with certain key enhancements to improve performance
and reduce the card logic required to drive the backplane. The
high-speed bus will hereafter be referred to as the "bus".
The VME Bus
was introduced as a multimaster bus to allow cards
in a system to interface with one another and to share global
resources. The VME Bus is a complete specification which includes
mechanical, electrical, and protocol specification.
mechanical specification defines backplanes, card sizes and
electrical specification defines drive capability, as well
as timings for all backplane signals.
Note that the
VME Bus is not a clocked system and that maximum
rise and fall times are not specified. Instead, it specifies
electrical characteristics for drivers and receivers. The current
drive specified for circuits driving control signals was defined at
either 64 ma (tristate signals), or 48 ma (open collector signals).
The high current drive, combined with the proper terminating resistor
value, is required or a number of reasons. First, the large current
value is required to satisfy input current requirement for bus signal
receivers on other cards. Second, the combination large current
value and a low terminating resistor value provide the high state
pull-up for open collector signals and aid in restoring the tristate
control lines to a high value.
specifies a number of cycles that can take place
over the bus. All cycles are initiated by a bus master and usually
involve a slave.
- READ/WRITE/INTERRUPT ACKNOWLEDGE CYCLES
A bus master
initiates a cycle by applying proper address,
data, and control signals, and waits for the appropriate slave to
complete the cycle.
- INTERRUPT/INTERRUPT ACKNOWLEDGE CYCLES
can be passed over the backplane to the CPU and an
interrupt acknowledge cycle is defined over the bus.
- ARBITRATION CYCLES
masters can request the bus and be granted bus
mastership after proper handshake.
- BLOCK TRANSFER CYCLES
A bus master
can access a contiguous area in global memory by
supplying the starting address to the appropriate slave and then
repeatedly handshaking control signals in response for each data