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Method for coherent interrupt handling Disclosure Number: IPCOM000109309D
Publication Date: 2005-Mar-23
Document File: 6 page(s) / 115K

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The Prior Art Database


Disclosed is a method for coherent interrupt handling. Benefits include improved functionality, improved performance, and improved reliability.

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Method for coherent interrupt handling

Disclosed is a method for coherent interrupt handling. Benefits include improved functionality, improved performance, and improved reliability.


              A network interface card (NIC) that is connected to a PC generates interrupts when an input/output (I/O) event related to an operation occurs. For example, when packets are received from the network, packet transmission is completed or a network link is lost.

              Each transmission (Tx) packet and every received (Rx) packet typically has its own descriptor in host memory that points to the packet buffer and stores packet information. The descriptor includes the ownership status. The NIC hardware (HW) owns the message when it controls the transaction. During Tx, ownership returns to the host software (SW) when the packet buffer and descriptor done being used by the HW and the host can make new use of them. During Rx, ownership changes to SW when a packet is in the buffer and the message can undergo further SW processing.

              In a high-speed network, a high interrupt rate to the operating system (OS) driver is expected. To reduce the interrupt rate, different interrupt moderation schemes are applied to the NICs. For example, in one interrupt, the host CPU processes several Tx or Rx packets. As a result, the OS does not perform a context switch to its interrupt service routine for every packet.

              Conventional receive packet processing begins when the NIC interrupts the host CPU after one or more packets are received and placed in host memory. The descriptors change the status of the receive buffers to report a valid packet in the buffers. The interrupted OS stops its current operation and switches context to the NIC’s driver interrupt service routine (ISR). It reads the NIC’s interrupt cause register (ICR) to check for the interrupt reason. The read of this register may block further NIC interrupts until the driver is complete, depending on the implementation. In some implementations, the NIC’s driver ISR may write to an interrupt mask register to disable further interrupts from the NIC until processing is complete (see Figure 1).

              In another implementation, the ISR dispatches a deferred procedure call (DPC) to execute as a continuation of the interrupt handling that is performed in a noninterrupt context. When the DPC executes, it processes all the received packets that it finds in the host memory, including those that are received after the original interrupt has been generated. The DPC clears the ICR to acknowledge the receive processing and enable the device interrupts by writing to the device’s interrupt mask register. (The last two writes may be combined to a single equivalent write in some implementations.) When the write is complete, the DPC ends.

Race conditions

              Classical race conditions occur between the driver’s DPC and the NIC when the driver detects that no more received packets...