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Chip Corner and Edge Reinforcement Structures to Prevent Low-k Chip Cracking Disclosure Number: IPCOM000109770D
Original Publication Date: 2005-Mar-24
Included in the Prior Art Database: 2005-Mar-24
Document File: 2 page(s) / 12K

Publishing Venue



A multilevel metal crackstop is designed to prevent dicing damage, cracking, and delaminations in packaged IC chips with low-k dielectrics in the BEOL. This design includes vertically-aligned dummy metal shapes connected with dummy vias, and a single or multi-walled solid stripe connected at line and via levels which follows the chip perimeter and especially extends out to the chip corners. Other multilevel-connected metal alignment marks and moisture/oxidation barriers can also be added to provide redundant protection against such mechanical failures.

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Chip Corner and Edge Reinforcement Structures to Prevent Low-k Chip Cracking

As semiconductor industry is moving to reduce capacitance between wiring, silicon oxide is replaced by a low-k material often with lower fracture toughness. The chips with such materials are susceptible to dicing damage, which causes failure during chip packaging and testing. The situation becomes worse for ultra low-k materials. The invention is proposed to lay out chip corner and edge structures to reduce dicing damage and toughening back ene of line fracture resistance.

The corners of a chip are the most vulnerable locations for dicing damage and cracking. The invention is to reinforce the corners with stiff copper structures that connects from substrate to top passivation. Such structures can also be placed along chip edges to prevent dicing damage and cracking from there. These structures can be either dummy or functional. First one or more crack stops are placed along chip edges, and at chip corners one or more lines that connect from edge to edge to form a triangular region where dummy structures fill.

Since copper is a tough and ductile compared to low-k materials, using it to make stiff structure around corners and edges can toughen the back end of line and protect chip functions inside.


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