Planarized Metallized Field Effect Transistor
Original Publication Date: 1992-Oct-01
Included in the Prior Art Database: 2005-Mar-25
A technique is described whereby a field-effect transistor (FET) structure and fabrication process provides the ability to convert source-drain epi and gate poly-silicon to tungsten in one step, thereby lowering the sheet resistance. Minimal differential height between source and drain is produced.