Original Publication Date: 1992-Sep-01
Included in the Prior Art Database: 2005-Mar-25
Bullions, RJ: AUTHOR [+5]
The present invention enables implementation of complex functions in a large, hardware-controlled, pipelined, general-purpose digital computer without incorporating a microprocessor into its design. The invention solves the problem of implementing these functions in this type of computer with the flexibility provided by firmware and avoids packaging problems introduced by the inclusion of microprocessor hardware.
invention enables implementation of complex
functions in a large, hardware-controlled, pipelined, general-purpose
digital computer without incorporating a microprocessor into its
design. The invention solves the problem of implementing these
functions in this type of computer with the flexibility provided by
firmware and avoids packaging problems introduced by the inclusion of
invention uses the preexisting dataflow and
hardware controlled execution units of an otherwise conventional
pipelined processor to accomplish complex functions. Additional
hardware controlled instructions (private milli-mode only
instructions) are added to provide control functions or to improve
performance. These private milli-mode instructions augment the
architected instruction set. Milli-mode routines can intermingle the
milli-mode only instructions with architected (macro-mode)
instructions to implement complex functions.
of the present invention is illustrated in the
figure. As is conventional, the illustrated computer system includes
a system storage (main memory) 134 and a cache memory subsystem
(cache) 112. The system storage 134 contains the macro-instructions
(e.g., System 370 or System 390) that the processor is executing as
well as the data those instructions are manipulating. It also
contains the system area (memory outside of the program addressable
storage) that is used by the millicode (and has other uses). The
cache memory subsystem 112 is of a conventional combined
data/instruction cache type including conventional cache control
logic (a split cache could be used as an alternative). The cache 112
includes a copy of the macro-instructions that the processor is
executing as well as the data those instructions are manipulating.
registers 100 are connected to receive instructions
from the cache memory subsystem 112 and from a Millicode Array 106.
The instruction registers 100 are input registers for the decoder
102. Instructions are parsed and placed into the instruction
registers (I-REGS). The decoder 102 reads the contents of the
I-REGS, decodes the instruction (or causes an operation exception),
and schedules the instruction for execution at one or more of the
hardware execution units 104.
array 106 contains a set of milli-routines.
milli-routine implements one or more of the complex functions or
instructions. The milli-instructions contained in these routines
consist of a mixture of regular macro-instructions and private
milli-mode only instructions. The private instructions provide
control functions needed by the millicode routines. The set of
millicode routines reside outside of program addressable storage.
fetch control logic (not shown) provides the
control logic that fetches instructions either from the cache 112 or
the millicode arra...