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Browse Prior Art Database

Buried Printed Circuit for Electrical Timing Characteristics in Multilayer Circuit Boards

IP.com Disclosure Number: IPCOM000110455D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 1 page(s) / 46K

Publishing Venue

IBM

Related People

Calabrese, G: AUTHOR [+2]

Abstract

Disclosed is a technique to precisely characterize electrical timing parameters on multiple layered printed circuit boards.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Buried Printed Circuit for Electrical Timing Characteristics in Multilayer Circuit Boards

      Disclosed is a technique to precisely characterize electrical
timing parameters on multiple layered printed circuit boards.

      Referring to Figure 1, circuit board 1 is shown with buried
printed circuit 2 fabricated in a contiguous manner.  Each circuit
path section S1 - Sn is buried on individual signal circuit planes S1
- Sn, as shown in Figure 2.  Timing characterization circuit paths S1
- Sn have endpoints which are attached to connectors to permit
testing external to the circuit board.  In this manner, each section
S1 - Sn of the multilayer printed circuit board can be characterized
for all electrical parameters which affect signal speed & timing.
This would facilitate the alteration and/or customization of external
modules and cable assemblies to exact matching electrical
characteristics for optimum system performance.

      Disclosed anonymously.