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An Alternative Design for Array Fault Tolerance

IP.com Disclosure Number: IPCOM000110460D
Original Publication Date: 1992-Nov-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 1 page(s) / 49K

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McGilvray, BL: AUTHOR [+2]


This design addresses recovery from a solid error in a sequential aligned array.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 89% of the total text.

An Alternative Design for Array Fault Tolerance

      This design addresses recovery from a solid error in a
sequential aligned array.

      In arrays designed wherein every element in the array is
critical data and the data is used in a sequential manner, a solid
error in any element of the array makes it non-functional.  Error
correcting codes (ECC) or a redundant array will allow correction of
single-bit errors or one single 2-bit error.

      This design describes an array that has unused elements within
the array.  For example, the array has 256 elements; however, only
200 elements are used.  The array is also accessed with intelligent
microcode that has access to the array to refresh the array.  When
the hardware using the array fetches an element of the array and an
error is detected, a service processor is signaled, reporting the
failing address within the array.  The service processor will then
place the failing address in a sparing table within the microcode
storage and signals the microcode to refresh the array.  Microcode,
recognizes there is a failing address in the sparing table, and will
refresh the array by passing the failing address(es).  It will also
set a starting address in a separate hardware register for the
hardware to use as the starting address so as to bypass any failing
elements at the beginning of the array.  Microcode will place a skip
command within the data field of the element preceding the address
that is failing.  Th...