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Wafer Burn-in

IP.com Disclosure Number: IPCOM000110627D
Original Publication Date: 1992-Dec-01
Included in the Prior Art Database: 2005-Mar-25
Document File: 2 page(s) / 67K

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Related People

Gruber, HW: AUTHOR [+4]


This article describes a semiconductor device, such as a memory chip, and a method of burning in same.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 100% of the total text.

Wafer Burn-in

       This article describes a semiconductor device, such as a
memory chip, and a method of burning in same.

      A memory chip known per se is modified to be retained in wafer
form until memory card assembly.  Fig. 1 shows a portion of a wafer
having an array of memory chips thereon.  The kerf area between the
memory chips is enlarged, so that the I/O pads of the memory chip as
well as the burn-in test circuitry are placed in this enlarged kerf
area.  The test circuitry wiring to the memory chip interface
circuits is designed such that dicing the wafer into individual chips
disconnects the on-chip test circuitry (burn-in generator in Fig. 1)
from the memory circuitry by cutting the wiring.  The I/O pad wiring
to the chip memory circuitry is on an additional metal layer.  The
active chip areas are covered by polyimide epoxy which is
personalized to provide access to the I/O pads.

      Burning-in is effected on wafer level by a test plate with
three needles per chip, as shown in Fig. 2.  The self-generated heat
is part of the burn-in power monitored by a temperature-controlled
plate on which the wafers are mounted.

      After burn-in and dicing the wafer, the memory chip is directly
usable as a memory module, because the I/O pads are placed in the
enlarged kerf area.  A plurality of memory chip modules can be put
together to form a stack assembly, a D-ZIP (zig-zag in-line package),
a wire bond memory block, or the like.