Defect Free Isolation Process for Substrate Plate Trench Dynamic Random Access Memory Cells

Defect Free Isolation Process for Substrate Plate Trench Dynamic Random Access Memory Cells

       Described is a fabrication process which allows the use
of the conventional local oxidation (LOCOS) process for device
isolation in a dynamic random access memory (DRAM) using substrate
plate trench (SPT) cells.

      The method described herein improves on a prior-art process
that caused SPT DRAM cells to be prone to dislocations in the storage
mode diffusion when LOCOS was used for isolation, causing high
leakage currents and unacceptable retention time.  Fig. 1 shows a
cross-section of the SPT cell and Fig. 2 shows the top view of the
SPT cell.

      It has been determined that the dislocations are a result of
LOCOS grown on top of the polysilicon-filled trench (PFT) adjacent to
a p+ diffusion found in a SPT cell array.  The dislocations appear
immediately after the p+ (boron) junctions are implanted and
annealed.  The growing LOCOS on top of a PFT leads to high stress,
but not enough to cause dislocations alone.  As the LOCOS grows, it
tries to lift up the Si3N4 layer that protects part of the PFT and
the active device area.  The growing LOCOS pushes up on the Si3N4 and
also down on the polysilicon filling the trench.  This leads to high
stress in the silicon adjacent to the PFT.  When boron is implanted,
the residual implant damage, in conjunction with the already present
stress, allows the dislocations to grow during the subsequent high
temperature anneals.

      The concept described herein implements a process that relieves
the stress by inserting a high temperature anneal after the LOCOS has
been grown and after the LOCOS nitride has been stripp...