A Method of Handling Gaps in Subscripted (Stranded) Simulation Nets

A Method of Handling Gaps in Subscripted (Stranded) Simulation Nets

      Disclosed is an efficient method of handling subscripted
(stranded) simulation nets that have no actual hardware logic driving
the nets so that the nets can be referenced, altered, or displayed,
without having to generate any real simulation logic to represent the
gate. In hardware design languages, it is often convenient to bundle
similar nets.  The individual nets are referenced as a subscripted
(stranded) name, for example, RAM_RAS(7).  In some cases, there will
be gaps in the subscripts, for example, when subscripts of one bundle
are matched with subscripts of another associated bundle of a
different length.  In these cases, one or more subscripted nets of
the smaller bundle are not described in the hardware logic (since
there is no actual hardware logic associated with that net), but
their existence will be implied by the existence of higher
subscripts, for example, RAM_RAS nets 0 to 2 and 5 to 7 may exist,
but nets 3 to 4 do not.

      During simulation, it is convenient to refer to the entire
bundle of nets by using the bundle name, ie., using RAM_RAS to mean
all the nets in the bundle RAM_RAS.  The simulator must be able to
access the value of the nets in RAM_RAS, even though there are gaps
in the net subscript range.

      One way of handling this is to generate a simulatable gate for
all of the nets, regardless of whether they truly exist.  However,
this may be wasteful in terms of storage or access time depending on
a gi...