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# Nonlinear Impedance Used for Signal Compression in Receiving Amplifiers

IP.com Disclosure Number: IPCOM000110793D
Original Publication Date: 1994-Jan-01
Included in the Prior Art Database: 2005-Mar-26
Document File: 2 page(s) / 49K

IBM

## Related People

Conner, DE: AUTHOR

## Abstract

Described is a circuit arrangement which protects a receiver amplifier from an overdriven condition. A nonlinear impedance is placed in series with each leg of the input circuit of a differential amplifier. The volt-ampere characteristic of this impedance is constant between a pre-determined current threshold. Beyond the threshold, the impedance will increase proportionately with the voltage, and the resulting current will be essentially constant. Simply put, the non-linear impedance will behave as a resistive element of constant value when the input voltage across the device is less than the threshold. Beyond the threshold, the impedance will vary in proportion to the voltage.

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Nonlinear Impedance Used for Signal Compression in Receiving Amplifiers

Described is a circuit arrangement which protects a receiver
amplifier from an overdriven condition.  A nonlinear impedance is
placed in series with each leg of the input circuit of a differential
amplifier.  The volt-ampere characteristic of this impedance is
constant between a pre-determined current threshold.  Beyond the
threshold, the impedance will increase proportionately with the
voltage, and the resulting current will be essentially constant.
Simply put, the non-linear impedance will behave as a resistive
element of constant value when the input voltage across the device is
less than the threshold.  Beyond the threshold, the impedance will
vary in proportion to the voltage.  The result is an output signal
which is amplitude limited to the value of a current at the threshold
times input impedance of the differential amplifier.

Referring to the Figure, field effect transistors Q1 and Q2 are
chosen for Idss value that will provide the desired signal limiting.
This value will be equal to Idss(Rt).  Below the threshold voltage of
Q1 and Q2, the channel resistance of these devices is relatively low
and constant.  The channel resistance and R1 form a voltage divider
for the input signal.  The impedance curve of the FEt circuit of Fig.
1 is shown in Fig. 2.  The circuit takes advantage of the fact that
when the Vgs of a field effect transistor is held to zero, the drain
cur...