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Use of the SYNC Instruction to Synchronize Completion of Translation Look-aside Buffer Invalidate in a Multi-Processor System

IP.com Disclosure Number: IPCOM000112440D
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27

Publishing Venue

IBM

Related People

Authors:
Kaiser, JM Merkel, LJ Moore, CR Muhich, JS [+details]

Abstract

Disclosed is a hardware solution for synchronization of Translation Look-aside Buffer (TLB) shoot down in a Symmetric Multi-Processor System (SMP). By using the SYNC instruction in conjunction with the TLB Invalidate (TLBI) instruction, a method is described to ensure translation coherency among all processors that are contained within the SMP environment.