Breakup of Streaming Programmed I/O Transactions to Simplify Processor Design
Original Publication Date: 1994-May-01
Included in the Prior Art Database: 2005-Mar-27
Reese, RJ: AUTHOR [+3]
The following discloses a technique for handling streaming Programmed I/O (PIO) operations on a microprocessor.
Breakup of Streaming Programmed I/O Transactions to
discloses a technique for handling streaming
Programmed I/O (PIO) operations on a microprocessor.
processor design point that used a common bus for both
memory transactions and PIO operations, a method of handling
streaming PIO operations was needed that was consistent with the rest
of the processor design.
constraints from the processor design included multiple
word transfers (which move data between the bus and multiple
general-purpose registers) and handling unaligned data transfers.
The multiple word transfers required a close interconnection between
the memory bus and the registers in order to use a streaming protocol
on the bus (a single address cycle followed by multiple data transfer
cycles). This linkage was not already present in the design. For
unaligned transfers, methods of splicing data together from multiple
registers and placing them on the bus neither exist nor would they be
easy to implement because of the timing constraints on the bus. In
particular, the bus device could ask for data every cycle, whereas
the memory transactions only require accessing one register per
In order to
overcome the above constraints, sizeable amounts of
buffering and byte steering logic would be needed.
A solution to
the problem was developed that breaks up the
streaming operations and unaligned operations in...