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Bit Sparing Logic for Semiconductor Memory Systems Disclosure Number: IPCOM000112699D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 69K

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Related People

Coteus, PW: AUTHOR [+2]


Bit Sparing Logic for Semiconductor Memory System s = 2, d = 4

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Bit Sparing Logic for Semiconductor Memory Systems

    Bit Sparing Logic for Semiconductor Memory System
                     s = 2, d = 4

      Modern semiconductor memory systems contain hundreds of
megabytes of storage and are expected to be error-free for many
years, in spite of significant bit failure rates.  Error-Correction
Codes (ECC) can be used to give some protection against intermittent
bit failures (soft bit errors), but can themselves fail when
excessive numbers of bits fail permanently (hard bit errors).  We
describe a bit sparing architecture that allows wide data buses
and/or a large number of spare bits to be used to insure high
reliability, while maintaining a fast data path.

      The architecture for the simple case of a 4-bit data path with
2 spare bits is shown in the Figure.  There is a semiconductor memory
system, to which a memory controller writes, or from which it reads.
The ROM or RAM memory system may have separate read and write ports,
or common bidirectional ports.  The memory system may be a simple
array of semiconductor circuits inside the same semiconductor chip as
the memory controller, or a large number of memory chips with
supporting logic to provide a common Input/Output (I/O) interface to
the memory controller.  An access to the ROM or RAM memory transfers
d data bits and s spare bits between the memory system and a set of
Multiplexers (MUXes) (multiple input, 1 output logic unit) which lie
between the memory system and the memory controller.  There are
separate MUXes for the read and write path...