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JTAG Invalid State Off Chip Drive Protect Mechanism Disclosure Number: IPCOM000112905D
Original Publication Date: 1994-Jun-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 4 page(s) / 108K

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Related People

Noll, MG: AUTHOR [+2]


Disclosed is a circuit to guard against damage to a IEEE Std.1149.1 compliant component during test.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

JTAG Invalid State Off Chip Drive Protect Mechanism

      Disclosed is a circuit to guard against damage to a IEEE
Std.1149.1 compliant component during test.

      The IEEE Std.  1149.1 (JTAG) Test Access Port (TAP) and
Boundary-Scan Architecture specifies test circuitry which may be used
to verify the interconnections between integrated circuits on a
system board.  In particular, the documented SAMPLE/PRELOAD and
EXTEST instructions permit off-chip driving of preloaded values.
Thus, the potential exists of damaging system components via improper
enabling of off-chip drivers through the use of such test circuitry
during test.  This disclosure expands on this potential problem and
describes the solution adopted.

      The JTAG architecture specifies how a ring of boundary scan
cells can be placed around the periphery of a chip for internal and
interconnect testing.  Automatic Test Equipment (ATE) can, via a TAP:
load command instructions, load test vectors and shift out serially
the results of tests executed.  Four inputs, TMS, TDI, TRST and TCK
provide the required stimuli and control to the TAP and test logic.

      If the TAP controller is implemented as a One-Hot design (one
latch set per state), the potential exists for the TAP state machine
to jump to an invalid state from which it could not recover.  Only by
resetting the TAP via the TRST input would the state machine return
to an initial state.  In the meantime, given the static nature of the
test, and given that the invalid state would not be recognized by the
ATE, the Device-Under-Test (DUT) could, for very long periods of time
randomly enable off chip drivers, potentially damaging other system

      Fig. 1 illustrates a scenario where system components could
potentially be damaged.  In Fig. 1, BSC(i) represents a boundary scan
cell which controls the enabling of the Off Chip Driver through
multiplexer M1.  M1 allows the internal logic to control the driver
during functional mode.  During JTAG test mode, the TAP interface
controls test values driven off chip through M1.

      The value driven off chip is sourced...