Versabus Module Eurocard Bus Auto Slot Identification
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Publishing Venue
IBM
Related People
Betcher, CW: AUTHOR [+3]
Abstract
A logic circuit is disclosed which allows the Versabus Module Eurocard (VME) bus slot ID to be automatically assigned immediately after power on reset (POR). The circuit utilizes several of the VME bus arbitration control signals and a subset of the VME address bus to implement the function.
Versabus Module Eurocard Bus Auto Slot Identification
A logic
circuit is disclosed which allows the Versabus Module
Eurocard (VME) bus slot ID to be automatically assigned immediately
after power on reset (POR). The circuit
utilizes several of the VME
bus arbitration control signals and a subset of the VME address bus
to implement the function.
1. Upon power up,
all VME cards which require slot ID initialization
shall drive *BR3 active
("*" indicates an active low signal).
On
the slot 1 (arbiter) CPU, a five bit
counter, CTO (slot ID
counter), contains the binary slot ID
of the next card to be
initialized. This counter is set to a count of two by POR.
2. After POR goes
inactive, the slot 1 CPU arbiter ARBO detects *BR3
active, and drives *BG3OUT active in
accordance with the normal
VME bus arbitration protocol.
3. The next VME
card downstream ("VME card X") from slot 1 requiring
slot ID initialization detects *BG3IN
active. The leading edge
of *BG3IN sets DFFO in the slot id
logic for VME card X. Note
that devices not requiring slot ID
should simply pass through
*BG3IN as is.
4. A single pulse
of approximately 100ns is generated on *BBSY by
slot ID logic on VME card X (from
logic elements DF1-3, GT2-3).
The leading edge of *BBSY causes the
arbiter ARBO to disable
*BG3OUT. The trailing edge of *BBSY loads the value
from the
slot ID counter CTO into the slot ID
register RGO of VME card X.
Note that the...