Uninterrupted Multiple Bus Cycle Transfer Mechanism for Computer Systems
Original Publication Date: 1994-Aug-01
Included in the Prior Art Database: 2005-Mar-27
Casthely, FJ: AUTHOR [+3]
Described is an architectural implementation to provide uninterrupted multiple bus cycle transfers in computer systems supporting a restartable sequence of cycles. The technique features a means of optimizing aborted cycles by using lock architecture. System performance is improved by reducing the frequency of reissued cycles and by aborting only the first cycle of a sequence.
Uninterrupted Multiple Bus Cycle Transfer Mechanism for
an architectural implementation to provide
uninterrupted multiple bus cycle transfers in computer systems
supporting a restartable sequence of cycles. The technique features
a means of optimizing aborted cycles by using lock architecture.
System performance is improved by reducing the frequency of reissued
cycles and by aborting only the first cycle of a sequence.
In prior art,
processors utilizing restartable cycle
capabilities, such as a store-in cache controller, had the ability to
abort current cycles in progress and to reissue them at a later point
in time. This ability to abort cycles in progress was intended to
allow snoop cycles to enable cache write-backs of the highest
priority on a shared bus.
single cycle transfer could be broken down into
several smaller cycles, such as a thirty-two bit read from an eight
bit device. In the case of an Intel 486* processor code fetch, a set
of sixteen cycles must be run to an eight bit device in order to
satisfy the processor's request. In the prior art, a set of sixteen
cycles would consume a considerable amount of the time allocated to
the processor on the shared bus. Aborting such a long set of sixteen
cycles could affect system performance, particularly where fifteen of
the sixteen cycles had already been run. Therefore, a method was
needed to determine when a sequence of cycles was in progress and to
provide a mechanism by which this sequence of cycles is allowed to
run to completion.
controller is dual ported allowing the main memory
to be accessed by the Central Processing Unit (CPU)/cache complex, or
by the adapter card bus. Fig. 1 shows a block diagram of the dual
ported memory controller in a system architecture design. Memory bus
10 and adapter card bus 11 are shared by CPU/cache complex 12 with
memory controller 13 and bridge 14 acting as arbiters for each
respective bus. To facilitate arbitration, the 486 architecture
defines a signal called LOCK# to indicate that the processor is
running a read-modify-write cycle where the external bus, i.e., a
shared bus, must not be relinquished between the read and the write
uninterrupted multiple bus cycle transfer concept utilizes
this architecture by supporting the LOCK# signal in the memory
controller as a means of maintaining ownership of the memory, or
adapter card bus. Also, the architecture enables bus controller 15
and bridge 14 to be responsible for running the correct number of
cycles required to complete a CPU/cache, or adapter card transfer.
provides a means of insuring a lengthy sequence of
cycles is not aborted and restarted unnecessarily by using the
conventional LOCK # signal architecture. Fig. 2 shows a block
diagram of the how the concept is implemented. Two major elements
are used: Cycle...