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Floating Point Bypass Dataflow Disclosure Number: IPCOM000113708D
Original Publication Date: 1994-Sep-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 6 page(s) / 207K

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Elliott, TA: AUTHOR [+3]


The RISC System/6000*, RSC and PowerPC 601* microprocessor floating point units are all based around the 'Fused Multiply-Add'

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Floating Point Bypass Dataflow

      The RISC System/6000*, RSC and PowerPC 601* microprocessor
floating point units are all based around the 'Fused Multiply-Add'

(FMA) instruction, T = (A * C) + B (Fig. 1).  In general, all other
floating point instructions are a subset of the FMA.  For an add
instruction, T = A + B, we would simply set C = 1 and perform an FMA.
For a move instruction, T = B, we would set A = 0 with C then
becoming an arbitrary value.  A large amount of silicon and
complexity is involved when instructions do not conform to this
subset methodology.  For example, the RSC divide required recursive
additions based on a lookup table without using the writeback stage.
To do this, additional entry points were needed in both the alignment
shifter and Carry Save Adder (CSA) tree along with their associated
control.  Knowing this, an attempt is made to implement all
instructions as a subset of FMA.

      Problem - The above table does not take into account all the
'special data' problems involved in a full IEEE compatible floating
point unit.  The table below lists SOME of the special data problems
for the accumulate instructions (FMA, FMS, FNMA, FNMS), and the
operand settings required to produce the answer using an FMA type
operation.  The important thing to note is the settings in the table
below are only determined after all three accumulate operands have
been examined.
     # = normalized or denormalized number (i.e., not zero, infinity,
        or NAN)
    D# = denormalized number
   INF = infinity
     X = don't care
  P(A) = refers to the prenormalized version of the A operand
  P(B) = refers to the prenormalized version of the B operand
  P(C) = refers to the prenormalized version of the C operand
  note 1: prenormalization requires running the pipeline once for
  each operand to be normalized, and then actually executing the
  note 2: The table above only shows how the three operands are
  affected by the special data cases.  The control for the MADD
  array, adder/incrementer, normalizer, and rounder will also all
  be affected by forcing special cases through the main dataflow.

      An important thing to realize is the above table is only a
sampling of the 'special data' problems for a single instruction
group.  The list below summarizes the 'special data' problems
throughout the floating point instruction set.
  1.  Prenormalization: Architecturally, all denormalized operands
      arithmetic operations must be prenormalized prior to executing
      the instruction.
  2.  NAN's: When a NAN operand is encountered, that NAN must be
      quieted and passed as the result.  If multiple NAN's are
      encountered, a priority order of A, B, then C determines which
      NAN is used.
  3.  GNAN's: If an invalid operation exception occurs the result is
      generated QNAN.  Examples of invalid operations are...