Browse Prior Art Database

System Hardware and Process Improvements in Tetra Ethyl Ortho Silicate Vertical Thermal Reactor Application to CMOS 16 Megabit DRAM Chips

IP.com Disclosure Number: IPCOM000113760D
Original Publication Date: 1994-Oct-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 57K

Publishing Venue

IBM

Related People

Authors:
Raffin, P [+details]

Abstract

Disclosed is a process and tool interdependent device to have the best working conditions performance. The system is a Tetra Ethyl Ortho Silicate (TEOS) Vertical Thermal Reactor (VTR) used for CMOS V process requirements. With vendor original design, poor performances have been obtained and found to be a detractor of product final yield loss. System hardware changes have been done which involved readjustments in process to improve performances.