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Combined Clock Multiplier/Deskew Macro Disclosure Number: IPCOM000114046D
Original Publication Date: 1994-Nov-01
Included in the Prior Art Database: 2005-Mar-27
Document File: 2 page(s) / 74K

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Cecchi, DR: AUTHOR [+4]


Described is a circuit that provides a method of using the same macro to deskew as well as multiply clocks.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Combined Clock Multiplier/Deskew Macro

      Described is a circuit that provides a method of using the same
macro to deskew as well as multiply clocks.

      Microprocessors, memory controller, and bus interface chips are
constantly being designed at decreasing processor cycle times.  At
these cycle times, it is necessary to provide clock deskewing so all
chips are synchronous.  In addition to this, many processors are now
being designed to be used in multiple chip as well as single chip
configurations.  This also causes the designer to require clock
deskew for multiple processor designs as well as a PLL or frequency
synthesizer for the single chip application.  To compound matters,
existing integrated circuit testers cannot always supply the cycle
times necessary for adequate test, so in certain cases chip designers
are forced to add a PLL to their chip for test.  Having both a deskew
macro and PLL or frequency synthesizer separate increase power, die
size, complexity and cost.  PLL's are not desirable due to their
noise sensitivity.  This circuit provides a method of using a digital
macro to deskew as well as multiply clocks in single and
multi-processor configurations.

      In frequency multiplier mode, a cycle time T is fed into RCVR.
The signal is divided by 2 immediately for accurate symmetry, and M1
is selects the T*2 signal.  The signal then goes into the variable
delay chain where the sample latch, counter, decode logic and latches
set the delay across all N variable delay elements to be one-half the
T*2 signal or T.  For example, if 20 nS is input the T*2 signal would
be 40 nS, and the delay across N delay elements would be 20 nS.  If