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Algorithm for Quantifying Phase Jitter Rejection of a Phase Locked Loop

IP.com Disclosure Number: IPCOM000114355D
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Document File: 2 page(s) / 49K

IBM

Related People

Baumgartner, SJ: AUTHOR [+2]

Abstract

An algorithm to quantify how much reference clock phase jitter actually contributes to a Phase Locked Loop (PLL) output phase jitter is disclosed. This approach involves a hardware measurement of the reference clock using a single shot digitizing oscilloscope and the use of a computer mathematics program for processing the measured data.

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Algorithm for Quantifying Phase Jitter Rejection of a Phase Locked
Loop

An algorithm to quantify how much reference clock phase jitter
actually contributes to a Phase Locked Loop (PLL) output phase jitter
is disclosed.  This approach involves a hardware measurement of the
reference clock using a single shot digitizing oscilloscope and the
use of a computer mathematics program for processing the measured
data.

The algorithm developed takes data captured by a single shot
digitizing oscilloscope and calculates the PLL phase noise rejection
based on the loop bandwidth parameter of the PLL.  The captured data
is processed by a program that was written in Mathematica, Version
2.2.  The only inputs that the Mathematica program requires are the
input data file, sampling rate, clock frequency, and the loop
bandwidth of the PLL.  The procedure is as follows:
1.  Acquire a single-shot acquisition of the PLL reference clock.
A
digitizing scope with sufficient analog bandwidth, sampling
rate
and record length should be used.  A long record length is
necessary for low frequency characteristics of the jitter.
2.  Read the data into math program.
3.  Interpolate the times of the threshold crossings from the
sampled
data.
4.  Calculate each successive period.
5.  Calculate the mean of all the periods.
6.  Calculate the deviation from the mean phase with respect to
time.
This re...