Mechanism for Connecting to a Synchronous Time-Division Multiplexed Bitstream using Asynchronous Strobed Transfers
Original Publication Date: 1994-Dec-01
Included in the Prior Art Database: 2005-Mar-28
Bass, RH: AUTHOR [+3]
A mechanism for connecting a Digital Signal Processor (DSP) to a synchronous Time-Division Multiplexed (TDM) bit-stream is described. Native to the DSP is an asynchronous strobed interface which is used for this connection. The disclosed mechanism translates the asynchronous transfers from the DSP into the synchronous bit-stream required at the TDM interface.
Mechanism for Connecting to a Synchronous Time-Division
Bitstream using Asynchronous Strobed Transfers
for connecting a Digital Signal Processor (DSP) to
a synchronous Time-Division Multiplexed (TDM) bit-stream is
described. Native to the DSP is an asynchronous strobed interface
which is used for this connection. The disclosed mechanism
translates the asynchronous transfers from the DSP into the
synchronous bit-stream required at the TDM interface.
DSP has several interfaces integrated into the DSP
chip which are capable of connecting to analog codec chips. However,
it has no interfaces which are appropriate for TDM interfaces such as
ISDN. The analog CODEC interfaces use asynchronous strobed bursts of
data of which are clocked by the DSP. ISDN data must be clocked by
the ISDN network interface chip, and is a continuous stream of data.
Additionally, ISDN interfaces require synchronization to the
beginning of a TDM frame. In order to avoid developing a new chip to
support ISDN products based on Mwave, a logic circuit was designed
which converts the asynchronous strobed interface of the DSP into the
synchronous interface required by the ISDN interface chip.
interface chip provides the layer-1 functions of the
S/T interface to an ISDN Basic Rate Port according to the CCITT
recommendations I.430 and T1D1 Basic User Network Interface
Specification, respectively. The logic circuit disclosed will
convert the synchronous TDM interface of the ISDN chip into the
asynchronous AIC interface native to the Mwave DSP. In other Mwave
designs, this AIC interface is usually strobed (FSX) at 9600 Hz. In
the disclosed design, FSX is strobed at 32000 Hz in order to transfer
all of the data on the ISDN line. To insure that the 9600 Hz sample
rate remains available within the DSP, an internal counter option is
used to generate interrupts.
A pair of
FIFO circuits forms a data path between the DSP and
the ISDN interface chip. Data is transferred into and out of the
ISDN chip at 768 kilobits per second in each direction. This
interface groups 12 bytes (or time-slots) into a frame, with a frame
rate of 8 KHz. The first bit in every IOM-2** frame is marked by the
rising edge of FSC, an 8 kHz signal synchronizing the ISDN frame to
ISDN network timing. The DSP transfers its data simultaneously in
high-speed bursts using 16 bit word transfers. The AIC port bursts
each data transfer when FSX (The AIC transfer strobe) is asserted.
This signal is asserted at a 32 kHz rate. The FIFO logic parses the
12 byte IOM-2 frame into a 4 byte AIC frame using only the low byte
of each AIC transfer. The ISDN channel and control information
contained in the IOM-2 frame is illustrated in the Table. The data
in each row of the table is transmitted or received when FSX is
the DSP interface will automatically transfer data
between the AIC...