High Speed Hardware Exclusive OR Engine for Redundant Array of Inexpensive Drives Applications
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Islam, RS: AUTHOR [+2]
Disclosed is a hardware Exclusive OR (XOR) engine which performs up to 16 way block-wise XOR function for the Redundant Array of Inexpensive Drives (RAID) Applications.
High Speed Hardware Exclusive OR Engine for Redundant
Array of Inexpensive
a hardware Exclusive OR (XOR) engine which
performs up to 16 way block-wise XOR function for the Redundant Array
of Inexpensive Drives (RAID) Applications.
In the RAID
(Redundant Array of Inexpensive Drives)
application, particularly RAID 3 and RAID 5, the XOR function is an
essential function for parity striping and data reconstruction when
one of the drives in the array fails.
Functional Description - Fig. 1 illustrates the XOR
Engine and its interconnect functional partitions.
The disclosed XOR Engine supports the following
o XOR data blocks from a Scatter/Gather list of 2 to 16 source
o 32 bit wide XOR per cycle.
engine, once activated by programming, fetches the
first element of the Scatter/Gather List pointed by the
"Scatter/Gather List Address Register". The fetched element's
content (byte count, destination address, and source addresses) are
stored in a set of working registers. The data addressed by the
source addresses are read from the DRAM via the DRAM CNTL. As data
is read from the DRAM, the data in the Data Buffer (assuming valid
data, no XOR is done if it is the first time) is simultaneously read
out. Both the DRAM and Data Buffer's data are XORed and stored back
into the Data Buffer immediately overwriting the old data. These
READ-XOR-STORE operations are performed every cycle till all the old
data in the Data Buffer is replaced. The XOR engine interleaves the
READ-XOR-STORE operations from the programmed source locations. That
is, XOR one block of data from location i, then XOR another block of
data from location j, and so on until the last location then transfer
the XOR resultant to the DRAM's location addressed by the destination
address. This procedure is repeated until the instructed number of
bytes of the last element in the Scatter/Gather List are XORed. An
interrupt is asserted when the XOR engine's task is completed.
Fig. 2 shows
the Scatter/Gather List in the DRAM and the
address and control registers. The Scatter/Gather List is a
contiguous block of data consists of n number of elements. The
number of elements and the size of each element are determined by the
List Element Count and Element Size fields of the "Scallter/Gather
Control Register" respectively. The data buffers addressed by the
destination and source addresses can be scattered in the DRAM. All
of these data buffers are assumed the same size which are determined
by the byte count word of each element.
magnifies one of the element in the Scatter/Gather List
shown in Fig. 2 for illustration and explanation purposes. All
destination and source addresses are 4 byte aligned.
byte count the byte count determines the size of all data