Signalling a Peripheral Component Interconnect Bus Master to a Data Parity Error
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Bui, HQ: AUTHOR [+4]
Disclosed is a method to signal a PowerPC* system Peripheral Component Interconnect (PCI) bus master that data being returned is corrupt.
Signalling a Peripheral Component Interconnect Bus Master
to a Data
a method to signal a PowerPC* system Peripheral
Component Interconnect (PCI) bus master that data being returned is
In a desktop
PowerPC system, system memory parity is generated
and checked by the PCI Bridge and Memory Controller (PCIB/MC) buffer
chip ASIC, which is separate from the memory controller and PCI
control logic (in the control chip). On a memory read cycle mastered
by a PCI device, the memory data is valid one cycle before the
PARITY_ERROR_ signal has been generated by the buffer chip.
sample PARITY_ERROR_ from the buffer chip before
ending the data tenure (assertion of the TRDY# signal) would incur a
wait state, thus degrading system performance. Not sampling
PARITY_ERROR_ at all could cause corrupt data to the PCI device. A
protocol is needed to signal the PCI bus master that the data being
returned is corrupt.
implemented in the PCIB/MC control chip ASIC for
the desktop PowerPC system is to continue to drive the TRDY# on the
same bus cycle (earliest bus cycle) in which data is valid,
maximizing throughput and minimizing bus latency. The PCI bus
protocol calls for the device supplying the data to drive the parity
bit (even parity) on the bus cycle immediately following the
assertion of TRDY#.
In the event
that a parity error is detected for the system
memory read, the contr...