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# Low Power Sequencer Design Method

IP.com Disclosure Number: IPCOM000114781D
Original Publication Date: 1995-Jan-01
Included in the Prior Art Database: 2005-Mar-29
Document File: 2 page(s) / 42K

IBM

Ioki, K: AUTHOR

## Abstract

Disclosed is a sequencer design method to lower power dissipation of the circuit. The basic concept is to stop clocks as much as possible while the sequencer is in the idle state. This concept can be achieved by assigning bit patterns to each state so that the hamming distances between the idle state and the next states are short. The clocks for the flip-flops which correspond to the bits that have same value in the idle state and in the next states can be stopped while the sequencer is in the idle state. In addition, the number of state which has a transition from the idle state should be small.

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Low Power Sequencer Design Method

Disclosed is a sequencer design method to lower power
dissipation of the circuit.  The basic concept is to stop clocks as
much as possible while the sequencer is in the idle state.  This
concept can be achieved by assigning bit patterns to each state so
that the hamming distances between the idle state and the next states
are short.  The clocks for the flip-flops which correspond to the
bits that have same value in the idle state and in the next states
can be stopped while the sequencer is in the idle state.  In
addition, the number of state which has a transition from the idle
state should be small.

Fig. 1 shows a state transition diagram of the sequencer.
State 0 is an idle state and the sequencer has five states.  In order
to implement this sequencer, at least three bits are required.  If
<y1,y2,y3>=<0,0,0> is assigned to state 0 and <y1,y2,y3>=<1,0,1> is
assigned to state 1, the clock for y2 can be stopped when the
sequencer is in state 0.  But the clocks for y1 and y3 can not be
stopped because y1 and y3 changes when the transition from state 0 to
state 1 occurs.  This shows that the hamming distance between the
idle
state and the next state should be made shorter to stop more clocks.

Fig. 2 shows another state transition diagram.  State 0 is an
idle state again.  In this sequencer, there are two states which have
a transition from state 0.  This means the clock must be provided to
at least tw...