Improved Direct Memory Access Write Performance for a RS/6000 Graphics System
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Arimilli, LB: AUTHOR [+2]
Disclosed is a method for improved Graphics Direct Memory Access (DMA) write performance for a RS/6000* system.
Improved Direct Memory Access Write Performance for a
a method for improved Graphics Direct Memory
Access (DMA) write performance for a RS/6000* system.
Controller provides a Graphics I/O (GIO) bus interface
to the RS/6000 processor via the System I/O (SIO) bus for high
performance graphics support. The maximum transfer size on the GIO
bus is 32 bytes and the minimum DMA transfer size on the SIO bus is
64 bytes. Therefore, for each DMA write initiated by an adapter on
the GIO bus, the I/O controller has to do a read-modify-write
operation (a 64-byte DMA read from memory, modification of 1 to 32
bytes of the 64 bytes, and a 64-byte DMA write to memory).
on the GIO bus converts the DMA write packet that
software initializes into 32-byte or smaller transfers on the GIO
bus. The read-modify-write penalty for DMA writes of less than 32
bytes or for DMA writes to non-consecutive addresses is unavoidable.
But, for DMA writes of 32 bytes to consecutive addresses, this
penalty is very costly. For example, if the software DMA write
packet length is one kilobyte (1K), then 32 32-byte transfers to
consecutive addresses are required on the GIO bus and this will
require 32 read-modify-write operations on the SIO bus (or a total of
64 64-byte transfers).
DMA buffers were implemented in the I/O controller
to solve the read-modify-write problem. For DMA writes of 32 bytes
to consecutive addresses on the GIO bus, the I/O controller assembles
two consecutive 32 bytes in its internal DMA buffers to form a
64-byte DMA write packet for the SIO bus. This way, for every two
32-byte DMA writes to consecutive addresses on the GIO bus, only one
64-byte DMA write operation is generated on the SIO bus instead of
two read-modify-write operations (two 64-byte DMA reads and two
64-byte DMA writes).
To make this
implementation workable, the I/O controller
maintains the dirty status of the 32 byte buffers. If the first DMA
write on the GIO bus is a 32-byte packet and 64-byte aligned, then
the I/O controller simply sto...