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Simplified External Circuitry to Generate Level Sensitive Scan Design Clocks

IP.com Disclosure Number: IPCOM000114955D
Original Publication Date: 1995-Feb-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 38K

IBM

Related People

Benayoun, A: AUTHOR [+2]

Abstract

Disclosed is a method for solving the following: Each gate array requires two clocks to operate. These clocks are called Level Sensitive Scan Design (LSSD) clocks and have to be generated on the board. The design is usually based on discrete circuits such as AND gates, OR gates... . The advantages of the current solution are the following: o Very small amount of logic to generate the two LSSD clocks minimizing the delay problem o Each LSSD clock can be tuned externally o One common set of LSSD clocks for all the gate arrays on the board

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Simplified External Circuitry to Generate Level Sensitive Scan Design
Clocks

Disclosed is a method for solving the following:  Each gate
array requires two clocks to operate.  These clocks are called Level
Sensitive Scan Design (LSSD) clocks and have to be generated on the
board.  The design is usually based on discrete circuits such as AND
gates, OR gates... .  The advantages of the current solution are the
following:
o  Very small amount of logic to generate the two LSSD clocks
minimizing the delay problem
o  Each LSSD clock can be tuned externally
o  One common set of LSSD clocks for all the gate arrays on the
board

This invention can be used for any hardware design based on gate
arrays.

Hardware Design - The logic to generate the two LSSD clocks is shown
in Fig. 1.

Notes:

1.  The delay is equal to the period of the system clock divided by
four
2.  The XOR between the delay chip and the input lead -A/B of the
multiplexer is implemented to provide in-phase signals to the
inputs of the multiplexer
LSSD Clocks Timing is shown in Fig. 2.