Bus Arbitration on the Integrated Command Data Bus for an Asynchronous Transfer Mode Adapter Adapter
Original Publication Date: 1995-Mar-01
Included in the Prior Art Database: 2005-Mar-30
Droz, TL: AUTHOR [+3]
Disclosed is an architecture for bus arbitration on the Integrated Command Data (ICD) bus for an Asynchronous Transfer Mode (ATM) adapter. This architecture quickly resolves the request for access to the ICD bus from multiple bus masters for burst data transfers.
Bus Arbitration on the Integrated Command Data Bus for an
Transfer Mode Adapter Adapter
an architecture for bus arbitration on the
Integrated Command Data (ICD) bus for an Asynchronous Transfer Mode
(ATM) adapter. This architecture quickly resolves the request for
access to the ICD bus from multiple bus masters for burst data
invention was designed to allow the use of the IBM*
developed Maunakea 32 bit Micro Channel* bus master system interface
module in an ATM environment. The Maunakea module interfaces to the
Micro Channel bus on one side and translates it into the ICD bus on
the other. The ICD bus allows for multiple bus masters and slaves.
This invention resolves the multiple requests for the bus and grants
the winner access within one 33 MHz clock cycle.
Due to the
bursty nature of data communications, it is not
efficient to only grant bus access for one transfer of data.
However, it is also not efficient to allow the current bus master to
have unconstrained access to the bus. In this invention, a design
that optimizes the number of data transfers from each bus master for
this type of communications link is described.
As shown in
Fig. 1, this adapter architecture has five ICD bus
masters, two transmit channels (for different priority traffic), one
receive channel, a local processor and the Maunakea module. Each of
these bus masters requests ICD bus access from the arbitration unit.
When granted, the current bus master uses either direct memory access
or single cycle operations to transfer data into or out of the data
cell memory. This invention describes the arbitration algorithm used
in this system. The Maunakea module is granted the highest priority
in this system. This is due to it's limited FIFO buffer size and the
fact that it is multiplexing both transmit and receive traffic flows
into a half-duplex Micro Channel bus. Whenever the Maunakea module
requests the bus, it obtains entry on the next available access
window. The remaining four devices all share access using a method
called "Multi-Level Arbitration with Second Level Priority Encoding
and Rotating Highest Priority Round Robin Pointer."
arbitration control module has five input request
lines, five output grant lines and assorted control, address and data
lines from the ICD bus and the data cell memory. Inside the
arbitration module are access transfer count registers for each ICD
bus master. These registers are set up by the local proc...