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Integrated Set of Design Verification Tools

IP.com Disclosure Number: IPCOM000115526D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 149K

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Rodriguez, JR: AUTHOR


Disclosed is a set of tools for the verification of the design of a computer component at various stages of product development.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Integrated Set of Design Verification Tools

      Disclosed is a set of tools for the verification of the design
of a computer component at various stages of product development.

      Fig. 1 is a block diagram showing a conventional Very
High-speed integrated circuit Hardware Description Language (VHDL)
model of the Unit Under Test (UUT) 1 and the VHDL test bench 2.  The
test bench 2 connects to the external interface 3 of the model 1,
providing the external environment to the model.  For design
verification, test bench 2 is used to apply the test stimulus to the
model 1 across the signals in the interface 3, which carries external
signals defined in the VHDL entity.

      Fig. 2 is a block diagram showing the relationships among the
various tools in the presently disclosed set as they are applied to
various environments.  Design verification and product test are more
effective when a test performed at each succeeding phase of the
process is a regression test using a set of tests from the previous
phase.  Therefore, the test tools provide a set of test cases that
can be used at various stages of product development, including
architecture verification 4, a first design verification test 5, a
second design verification test 6, and hardware product and system
tests 7.  In this process, the set of test cases 9 are ported to
different environments.  For example, VHDL test cases are translated
in translator 10 to execute on a host computer 11, and are used
without translation in a simulator environment 12.  Regression
testing is provided, first in simulators and subsequently on the
hardware implementation of the design, with the same test case suite.

Program tools are used to translate the format of the test cases to
that of the test environment.

      With this approach, the productivity achieved using any one set
of tests is applied across a wide range of test tools and
environments.  To achieve this effect, architecture verification and
design verification are based on a VHDL simulator.  The model, test
bench, and test file are portable to any design system compatible
with VHDL 1076.  The VHDL test bench 13 emulates the hardware tool
processor unit, issuing a command st...