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Arbitration for a PowerPC CPU Bus/PCI Bus System Disclosure Number: IPCOM000115550D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 82K

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Related People

Bui, HQ: AUTHOR [+5]


Disclosed is an arbitration scheme for a PowerPC* system utilizing a PCI expansion bus.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Arbitration for a PowerPC CPU Bus/PCI Bus System

      Disclosed is an arbitration scheme for a PowerPC* system
utilizing a PCI expansion bus.

      A unique arbitration scheme is required for a PowerPC system
utilizing a PCI expansion bus.  In a PowerPC system, the CPU
interface bus and the PCI bus are viewed as a single bus by the
arbiter (i.e., there is only one bus master at any one time on either
bus).  In addition, the arbitration scheme must address a number of
unique requirements and stipulations:
  o  Arbitration of the PCI bus devices must conform to the PCI bus
      specification 2.0.
  o  Arbitration of the CPU and optional L2 copy-back cache must be
      compliant to the PowerPC 60x bus specification.
  o  Devices must not be granted ownership of a bus while a cycle
      initiated by a master on a second bus is still in progress.
  o  Refresh of system memory DRAM must be supported as the highest
  o  The number of request/grant pairs (supported devices) must be
      easily increased or decreased.
  o  Logic for each supported device should consume only two latches
      in the logic.

The arbitration scheme implemented in the control chip of the PowerPC
PCI Bridge and Memory Controller solves these problems and

      Based on the number of requests active at any time, the arbiter
will grant based on the following guidelines:
  o  If no masters are requesting the bus, the bus will remain parked
      on the CPU.  PCI_AD and other required lines on the PCI bus
      be driven to a known state by the arbiter.
  o  If only one request is active, that master will be granted the
      bus for as long as the request is active, unless a second
      is asserted or refresh is required.
  o  If two or more requests are active: On the bus cycle that more
      than two requests are detected on the bus, those requests will
      latched.  All other requests (except memory refresh) occurring