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Memory-Mapped PCI Configuration Cycles Disclosure Number: IPCOM000115558D
Original Publication Date: 1995-May-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 2 page(s) / 41K

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Curry, SE: AUTHOR [+3]


Disclosed is a method to generate PCI configuration cycles on desktop PowerPC* systems.

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This is the abbreviated version, containing approximately 100% of the total text.

Memory-Mapped PCI Configuration Cycles

      Disclosed is a method to generate PCI configuration cycles on
desktop PowerPC* systems.

      The PowerPC Reference Platform contains a PCI bus which must
run a special cycle, called a configuration cycle, before running
normal data transfer cycles.  In the PowerPC Reference Platform, one
of the ways this cycle is implemented is through memory mapping.
This results in a simple, low-cost solution.

      By mapping PCI configuration cycles into separate memory pages,
the pages can be protected.  The operating system may protect PCI
configuration cycles from user code by marking all pages of memory
with addresses corresponding to configuration cycles as protected.

      PCI configuration cycle generation is illustrated in Fig. 1.
When the PowerPC chip generates an address, the PCI bridge examines
the incoming bits.  The high-order address decoder decodes the region
of memory assigned to a PCI configuration cycle (Fig. 2) and
determines whether a configuration cycle is to be generated.  If the
configuration cycle is called for, the cycle generator encodes the
PCI configuration cycle and sends it to the PCI bus.

      Next, the low order address decoder decodes bits 11 through
15 of the PCI address and sends an ID select signal (IDSEL) to the
correct PCI device.
  *  Trademark of IBM Corp.