Reduced Logic Data Alignment for Programmed Input/Output Store Transfer from the System Input/Output Bus to an Input/Output Bus
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Arimilli, LB: AUTHOR [+1]
Disclosed is a data alignment method for Programmed Input/Output (PIO) STORES which minimizes logic and physical design requirements.
Reduced Logic Data Alignment for Programmed Input/Output
from the System Input/Output Bus to an Input/Output Bus
a data alignment method for Programmed
Input/Output (PIO) STORES which minimizes logic and physical design
System I/O bus (SIO) provides the processor access
to the adapters on the I/O bus through the I/O controller (Fig. 1).
on the SIO bus is not address aligned as it is on the I/O bus.
the PIO Store data from the SIO bus is first address aligned using
rotate logic and then put in the I/O buffers in the I/O controller.
Since the data in the buffers is address aligned, it is transferred
without additional alignment onto the I/O bus (Fig. 2).
Data comes in
two forms on the SIO bus for PIO store
operations. String data is left justified on the SIO bus and
non-string data is right justified on the SIO bus. String data can
be from 1-127 bytes in length and non-string data can be 1 byte
(store byte), 2 bytes (store half word), or 4 bytes (store word) in
length. Two levels of muxing are required to address align the data
using the address, byte count, and string op fields (on the SIO bus
at the beginning of the data transfer) to generate the selects for
the muxes. These levels of muxing are different for the string and
non-string data, and therefore require an additional mux level to
pick string or non-string data into the I/O controller PIO buffers