Reduced Data Alignment Logic for Programmed Input/Output Load Transfer from an I/O Bus to the System Input/Output Bus
Original Publication Date: 1995-Jul-01
Included in the Prior Art Database: 2005-Mar-30
Arimilli, LB: AUTHOR [+1]
Disclosed is a data alignment method for PIO LOADS which minimizes logic and physical design requirements.
Reduced Data Alignment Logic for Programmed Input/Output
from an I/O Bus to the System Input/Output Bus
a data alignment method for PIO LOADS which
minimizes logic and physical design requirements.
System* I/O bus (SIO) provides the processor access
to the adapters on the I/O bus through the I/O controller. Data on
the SIO bus is not address aligned as it is on the I/O bus.
Therefore the PIO Load data from the I/O bus is stored in the I/O
buffers of the I/O controller address aligned. The address aligned
data is taken from the I/O buffers and sent through barrel rotate
logic before it is put on the SIO bus.
Data comes in
two forms on the SIO bus for PIO Load operations.
String data is left justified on the SIO bus and non-string data is
right justified on the SIO bus. String data can be from 1-127 bytes
in length and non-string data can be 1 byte (load byte), 2 bytes
(load half word), or 4 bytes (load word) in length. Two levels of
muxing are required to take address aligned load data from the I/O
buffers and realign the data for the SIO bus using the address, byte
count, and string op fields (on the SIO bus at the beginning of the
load request) to generate the selects for the muxes. These levels of
muxing are different for the string and non-string data, and
therefore require an additional mux level to pick string or
non-string data onto the SIO bus (Figs. 3A, 3B and 3C). Excluding
parity, the current data alignment data flow requires 16 8-bit/2-port
muxes, 4 8-bit/8-port muxes, and a 32-bit/2-port mux.
physical design/layout requires routing two 32-bit buses
into the mux feeding the SIO bus, another 32-bit bus which directly
onto the SIO bus, and two 32-bit buses into...