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Feedback Loop SCSI Driver with a Controlled Slew Rate Disclosure Number: IPCOM000116401D
Original Publication Date: 1995-Sep-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 6 page(s) / 212K

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Jasmin, J: AUTHOR [+2]


Disclosed is a driver circuit having a slew rate which is adjustable by changing the value of an external current source.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 31% of the total text.

Feedback Loop SCSI Driver with a Controlled Slew Rate

      Disclosed is a driver circuit having a slew rate which is
adjustable by changing the value of an external current source.

      Fig. 1 is a schematic view of a SCSI driver circuit implemented
in a Complementary Metal Oxide Semiconductor (CMOS-II) Application
Specific Integrated Circuit (ASIC).  In this circuit, transistors
TP0, TP1, T0, and T1 comprise a NOR gate having an output DBN, which
is low whenever the driver input is high, and high otherwise.
Transistors TP4 and T4 generate the inverted version of this signal,
DB.  Transistors TP2, TP3, T2, and T3 comprise a NAND gate having an
output KDRV, which is low only if the user master enable PB0 and the
manufacturing master enable DI are both high.  Transistors TP14 and
T14 invert KDRV, generating KDRVN.  Transistors TP15, TP16, T15, and
T16 comprise a NAND gate having an output DRVACN, which is low
whenever it is desired to use the sourcing (active negation for SCSI)
capability of the driver.  For this to occur, both master enables and
the negation enable PN0 must all be high.  Capacitors CFF and CFR
are, respectively, the feedback capacitors for the falling and rising
edges of the output transition.  TP28 is the current reference
transistor for current mirrors transistors TP19, TP20, and TP30.  A
current, about 20 microamps in this example, is sunk from PJ0 to
ground by a circuit external to the driver, to be described below.
This current controls the slew rate of the driver.  The slew rate is
about 0.2 v/ns (volts per nanosecond) per 20 microamps of current.

      Since the slew rate of the driver is adjustable by an external
current source, it is possible to reduce the current value to 1/100th
to 1/10th the value used in normal operation, correspondingly
increasing the transition time by a factor between 10 and 100.  When
this is done, the slew rate of the driver can be verified using a
polling tester.

      The falling edge transition of the output signal will now be
discussed.  When it is necessary to drive this signal from a high to
a low level, DB becomes low, activating TP21 to allow current to flow
from mirror transistor TP20 into current reference transistor T25.
This current is in turn mirrored by T26 to TP22, which in turn is
mirrored and increased by a factor of 15 times by TP23.  This
amplified current is used to charge the gate of the output assertion
transistor, TOUT.  When the gate voltage of this output transistor
reaches a turn-on threshold, about one volt in this example, the
output voltage at P10 begins to drop.  At this point, current begins
to be extracted from the top electrode of feedback capacitor CFF at
the rate given by Equation 1.  When this current reaches a level
greater than that of the current supplied to T25 by TP20, T25 and T26
are turned off, therefore turning off TP22 and TP23 to deprive the
gate of TOUT from an additional gate voltage increase.  In this way,