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VHDL Cycle Simulation Performance Improvement Disclosure Number: IPCOM000116593D
Original Publication Date: 1995-Oct-01
Included in the Prior Art Database: 2005-Mar-30
Document File: 4 page(s) / 93K

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Benayoun, A: AUTHOR [+5]


Disclosed is a System that increases a VHDL logic Cycle Simulation performance and efficiency.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

VHDL Cycle Simulation Performance Improvement

      Disclosed is a System that increases a VHDL logic Cycle
Simulation performance and efficiency.

      A logic described in VHDL is partitioned into several
functional islands which are developed in parallel by different

      A large part of the Development schedule is dedicated to
Simulation.  It begins on isolated islands, then goes up with larger
and larger structures to reach functions grouping different cards of
the future machine.

      There are Cycle Simulators which are more performing; their
principle is that the whole Logic is activated only at its own clock
cycle, no state change occurring between.  If all clocks are the
same, the Logic is activated each Simulation cycle which is equal to
the clock rate of the Logic; if not, the user must adjust all islands
clockings by calculating their HCF and converting their own cycle
according to it.

      All the islands are not ready to be connected at the same time
unless many of the problems occur on interfaces.  Thus at the
beginning of each project, a Simulation plan is established with the
definition of Simulation Devices ("Models") that represent subsets of
functions of the different interfaces to allow the Designers to
simulate their logic prior the one it really interfaces is available.
These Models are also described in VHDL.

      Two logics L1 and L2 are connected on both sides of a link S
with a specific protocol.  For example, bit time on S it is 240ns.
L1 is running at 30ns, L2 at 40ns.

      To simulate L1 and L2 independently one of the other, it is
necessary to develop a Link Model LM whose function is to send and
interpret data to/from L1 and L2 according to the protocol, until L1
and L2 are ready to be connected.

      It is difficult in terms of resources to develop two versions
of it and to maintain them.  Now, imposing it one of the 2 rates
would automatically degrade the Simulation performance with the logic
running with the other one:
  1.  If LM is clocked at 30ns, one simulation cycle represents
      o  30ns (Bit time/8) for L1 simulation, both L1 and LM being
          activated each cycle.
      o  10ns (HCF of 30ns and 40ns) for L2 Simulation, LM running at
          30ns having a cycle of 3 (i.e being activated each 3xN