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# Algorithm for VHDL Decision Path Recognition

IP.com Disclosure Number: IPCOM000116607D
Original Publication Date: 1995-Oct-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 6 page(s) / 119K

IBM

## Related People

Benayoun, A: AUTHOR [+3]

## Abstract

A piece of logic has Primary Inputs (PIs), Primary Outputs (POs), Latches and Internal Signals (Iss). The logic control flow is a series of decision elements. In VHDL, the decision elements are the: o case statement o if statement o conditional signal assingnment o selected signal assignment

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Algorithm for VHDL Decision Path Recognition

A  piece  of  logic  has  Primary Inputs (PIs), Primary Outputs
(POs), Latches and Internal Signals (Iss).  The logic control flow is
a series of decision elements.  In VHDL, the  decision  elements  are
the:
o  case statement
o  if statement
o  conditional signal assingnment
o  selected signal assignment

The  series  of  decision  elements  of  the  Control  flow are named
"PATHS".  They can go
o  from P.I to Latch
o  from P.I to P.O
o  from Latch to Latch
o  from Latch to P.O

The purpose of this disclosure is the  algorithm  to  recognize
all the "paths" defined in a VHDL description

A signal is "assigned" when it is the result of a boolean (AND,
OR, XOR, NAND,...) or arithmetic (+, -,...) operation.  It is
basically
the output of a logic function.

A signal is "referenced" when it is used to build another
signal by one of the above operations.  It is basically the input of
a logic function.  Referenced signals can be found in  both "ASSIGN"
(sigA=sigB references sigB) and "DECISION"  (If  sigA=1... references
sigA) type VHDL statements.

The  VHDL  source  code is parsed to recognize the PIs, POs and
latches and the decision elements are translated in  an  intermediate
format that will ease the encoming treatment.
Entity SAMPLE is
Port (
Signal E1    : IN STD_Logic ;
Signal Count : IN STD_Logic_vector(0 to 1) ;
Signal S11   : OUT STD_Logic ;
Signal S12   : OUT STD_Logic ) ;
End SAMPLE;
Architecture SAMPLE_A of SAMPLE is
Signal A   : STD_Logic ;
Signal C1  : STD_Logic ;
Signal C2  : STD_Logic ;
Begin
P1: Process(E1)
C1=0;
C2=0;
If E1=1 then
C1=1;
A=1;
Else
C2=1;
A=0;
End if;
End Process P1;
P2: Process(Count)
Case Count is
When "00" => If C1=1 then
S11=1;
End if;
When "01" => If C1=1 then
S11=0;
End if;
When "10" => If C2=0 then
S21=1;
End if;
When "11" => If C2=1 then
S21=0;
End if;
End case;
End Process P2;
End SAMPLE_A;

Phase 2 - All Temporary output ASSIGN statements are a...