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# Method for Increasing Usable Cycle-Time in Dynamic Circuitry Clocked by Phase-Lock Loops

IP.com Disclosure Number: IPCOM000117121D
Original Publication Date: 1995-Dec-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 67K

IBM

## Related People

Li, HH: AUTHOR [+3]

## Abstract

Disclosed is a method of eliminating dead-time due to clock variation which increases the amount of time for the logic to do the work. The slave clock frequency and placement is directly predictable in relation to the master clock. This scheme is independent of frequency and environment.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Method for Increasing Usable Cycle-Time in Dynamic Circuitry Clocked
by Phase-Lock Loops

Disclosed is a method of eliminating dead-time due to clock
variation which increases the amount of time for the logic to do the
work.  The slave clock frequency and placement is directly
predictable in relation to the master clock.  This scheme is
independent of frequency and environment.

As microprocessor speeds increase dramatically, the industry is
moving towards dynamic or "domino-like" circuit techniqes to provide
the speed needed.  However, dynamic techniques also have undesirable
drawbacks that limit the speed attainable.  A key drawback is the
dependence on clock jitter and duty cycle.  Essentially, this clock
cycle time.  This disclosure describes a method of eliminating the
heavy dependence on the clock shape and thus can provide significant
increase in machine speed.

A commonly used dynamic circuit family is 2-Phase domino logic.
In many cases, a phase-lock-loop (PLL) is used to generate the
machine clock which is then distributed to the logic where the second
phase is created through simple inversion.  The logic is split into
two portions: 1) the 1st portion evaluates during the first half of
the machine clock; and 2) the 2nd portion evaluates the second half
of the machine clock.  Precharge is performed during the other half
of the respective machine clock.  Duty cycle variation causes each
half of the machi...