DRAM Page-Mode Exit Determination

DRAM Page-Mode Exit Determination

      Disclosed is a method for determining when to exit page mode of
a page mode DRAM.  This method provides better average access time to
the DRAM than the simple methods of always staying in or always
exiting page mode after each DRAM access.

      Access time of DRAM is shortest for a page-hit (access to the
currently active DRAM row) when the DRAM is in page mode.  However,
access time is shortest for a page-miss (access to a different row
than the currently active one) when the DRAM is not in page mode.
Therefore, the average access time can be optimized by exiting page
mode when the next access is most likely to be a page-miss and
remaining in page mode when the next access is most likely to be a
page-hit.

      The PowerPC 601*, 603 and 604 processors running typical AIX*
applications operate in a manner such that their bus activity has the
following behavior: if a processor requests a memory reference and
then requests a second memory reference as soon as the first one
ends, then the second reference typically is a page-hit.  However, if
no request is made when the first request ends, then the next memory
reference is typically a page-miss (for page sizes of 8k bytes).

      The memory controller can be designed to take advantage of this
behavior.  Following each memory access, the memory controller
remains in page-mode (holds RAS# active) until the processor has had
sufficient time to make another request (t...