Differential Sense Bit-Line for Single-Ended Memory Cell Static Random Access Memory
Original Publication Date: 1996-Mar-01
Included in the Prior Art Database: 2005-Mar-31
Disclosed is a method to improve speed of a single-ended memory cell Static Random Access Memory (SRAM).
Differential Sense Bit-Line for Single-Ended Memory Cell
a method to improve speed of a single-ended memory
cell Static Random Access Memory (SRAM).
SRAMs were implemented with a single-ended memory
cell because of their read stability and high density. These designs
utilized the segmented bit-line structure to improve the access time
against the slowness of their full-level swing bit-line and output
bus characteristics as compared to the well known differential sense
bit-line of the double-ended memory cell designs.
uses a Dummy Bit-Line (DBL) as a reference sense
line for a group of differential sense amplifiers. The DBL is
implemented with the Nfet Relay Sense Circuit. The data storage
nodes of the Dummy memory cell (Dcell) are tied to power levels such
that the DBL is always pulled down as a read occurs. The RBL of the
accessed cell either stays at precharged (Vdd) level for reading a
'0' or it must be pulled down, at a faster rate than the rate at
which the DBL is being discharged, for reading a '1'. The difference
in the discharge rates of these bit-lines, RBL and DBL, develops a
differential voltage at the inputs of the Sense Amplifier (SA). When
the SET signal turns on, it drives the SA into active mode and the
differential voltage is amplified at the SA's outputs as OUT and OUTN
signals. This indicates that the reference (dummy) sense bit-line
provides a sin...