Level-Sensitive Scan Design Testing of Self-Resetting Complementary Metal-Oxide Semiconductor Circuits
Original Publication Date: 1996-Mar-01
Included in the Prior Art Database: 2005-Mar-31
Chappell, TL: AUTHOR [+1]
This disclosure describes solutions to problems encountered when LSSD test techniques were applied to self-resetting CMOS circuits designed for the Bellatrix/630 processor chip.
Level-Sensitive Scan Design Testing of Self-Resetting
Metal-Oxide Semiconductor Circuits
disclosure describes solutions to problems encountered
when LSSD test techniques were applied to self-resetting CMOS
circuits designed for the Bellatrix/630 processor chip.
Self-Resetting CMOS circuits designed for the Bellatrix/630
processor chip had some clocking characteristics that made it very
difficult to perform LSSD scan tests on these circuits. The
following is a summary of these characteristics:
a) The SRCMOS latches are precharged every cycle so that the latch
content, after being launched, would be reset due to the
precharge of the latch in preparation for next cycle
This resetting of the latch data was a problem during LSSD scan
testing because the latch, after being scanned with a
data value, would reset and the scanned data would be lost.
b) Because of the nature of the SRCMOS circuits, in that a
is needed on every cycle and because this precharge timing is
tied to the global clock that clocks the SR logic, it was
necessary to require the global clock, CLKG, to be free running
at all times so that the circuit performs as intended. This
requirement of having a free running CLKG caused a
synchronization problem because the launching clock, CLKL,
is derived from CLKG as shown in Fig. 1, could not overlap with
the rising edge of the scan clock to the master latch, CLKA.
CLKA was a lot slower than CLKG and had a somewhat sloppy
The problem was that the the rising edge of CLKA, if allowed to
overlap with CLKL, could cause some indeterminate latch value
be launched into the SR logic stages and invalidate the test
measurement taken at the receiving latch. Synchronization of
rising edge of CLKA with respect to CLKG and routing CLKA
the chip within a window accuracy of 200 ps was practically
impossible. The other option of delaying the rising edge of
until after the falling edge of CLKL was also extremely
to implement reliably.
c) The problem of orthogonal latches being scanned with
non-orthogonal test vectors. An orthogonal register is a
register that is restricted to containing only orthogonal data
vectors. An orthogonal data vector, in its simplest
is a vector of all 0s except for one and only one data element.
This definition can be extended to include all sorts of
restrictions as to what the data content of a register can be.
For example, a register of 8 bits can only acquire the
orthogonal data vectors 000000XX with bits XX being allowed to