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Fast Unsymmetrical Multiplier Logic with Distributed Booth Encoding and Prioritized Powering Disclosure Number: IPCOM000117623D
Original Publication Date: 1996-Apr-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 2 page(s) / 65K

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Gerwig, G Haas, J Koehler, T [+details]


In fast Floating Point Units, a Multiply Instruction has to be executed within one cycle. Consider a Multiplier of 61 x 61 bit. The state of the art solutions (Fig. 1) with an arraytype multiplier is too slow for the cycle. Another alternative with a customized multiplier array is uncertain in its result and needs very great effort (schedule and cost).