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Trash Addressing Mechanism Disclosure Number: IPCOM000117743D
Original Publication Date: 1996-May-01
Included in the Prior Art Database: 2005-Mar-31
Document File: 4 page(s) / 108K

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Aznar, A: AUTHOR [+4]


Disclosed is a circuit optimizing the use of asynchronous static RAMs.

This text was extracted from an ASCII text file.
This is the abbreviated version, containing approximately 52% of the total text.

Trash Addressing Mechanism

      Disclosed is a circuit optimizing the use of asynchronous
static RAMs.

      Asynchronous static RAMs utilization requires logic gating in
order to perform requested Write operations.  This gating, because of
timing dispersion, limits the cycle at which the RAM can be used.

      The proposed circuit suppresses any logic gating on the Write
Enable input and applies permanently to the Write Enable input a
cyclic Write Pulse.

      In the case no Write operation is needed, the circuit sets
the RAM address to a specified value which becomes unavailable to the
user.  This address is called the Trash Address.

      Fig. 1 illustrates the static RAM timing within the system
cycle along with the RAM write timing specifications.  Like with all
others asynchronous RAMs, the write operation is performed with help
of a WRITE ENABLE signal meeting all RAMs specifications:
  o  Write Enable (WE) minimum pulse width, referred to as Mpw.
  o  Address Set-Up time prior to WE activation, referred to as Tas.
  o  Address Hold time after WE de-activation, referred to as Tah.
  o  Data Set-Up time prior to WE de-activation, referred to as Tds.
  o  Data Hold time after WE de-activation, referred to as Tdh.

      The Write Enable must be timed correctly to ensure proper
RAM operation.  Respecting these specifications becomes harder as the
cycle time reduces.

      The Trash addressing solution consists in sending a Write
Enable Pulse (WE) directly on the Write Enable input of each RAM,
without any gating.

      This WE is generated by the clocking system, synchronized with
the system clock and timed within the second half of the cycle, as
depicted in Fig. 2.  Consequently, the first half of each cycle is
dedicated to READ operations, the second half to WRITE operations.

      The skew between WE and addresses or data is very well
controlled.  Both the system clock and the WE are generated by the
same clocking system and therefore, the skew between them is
guaranteed.  Then, by using the same kind of distribution resources
on the System Clock and the WE signal, the skew at RAM inputs between
WE (Writing of the RAM) and synchronous (System Clock) Addresses and
data is known and controlled.

      Fig. 3 depicts a typical implementation of the Trash Address
mechanism using the Xilinx XC400...